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1 v59c1512(404/804/164)qd high performance 512 mbit ddr2 sdram 4 banks x 32mbit x 4 (404) 4 banks x 16mbit x 8 (804) 4 banks x 8mbit x 16 (164) v59c1512(404/804/164)qd rev. 1.3 may 2010 537325a2519a ddr2-400 ddr2-533 ddr2-667 ddr2-800 ddr2-800 ddr2-1066 clock cycle time (t ck3 ) 5ns 5ns 5ns 5ns 5ns 5ns clock cycle time (t ck4 ) 5ns 3.75ns 3.75ns 3.75ns 3.75ns 3.75ns clock cycle time (t ck5 ) - - 3ns 3ns 2.5ns 2.5ns clock cycle time (t ck6 ) - - - 2.5ns 2.5ns 2.5ns clock cycle time (t ck7 )-----1.87ns system frequency (f ck max ) 200 mhz 266 mhz 333 mhz 400 mhz 400 mhz 533 mhz features - high speed data transfer rates with system frequency up to 533mhz - posted cas - programmable cas latency: 3, 4, 5, 6 and 7 - programmable additive latency: 0, 1, 2, 3, 4, 5 and 6 - write latency=read latency-1 - programmable wrap sequence: sequential or interleave - programmable burst length: 4 and 8 automatic and controlled precharge command - power down mode - auto refresh and self refresh - refresh interval: 7.8 us (8192 cycles/64 ms) - ocd (off-chip driver impendance adjustment) - odt (on-die termination) - weak strength data-o utput driver option - bidirectional differential data strobe (single-ended data-strobe is an optional feature) - on-chip dll aligns dq and dqs transitions with ck transitions - differential clock inputs ck and ck - jedec power supply 1.8v 0.1v - vddq=1.8v 0.1v - available in 60-ball fbga for x4 and x8 component or 84 ball fbga for x16 component - all inputs & outputs are compatible with sstl_18 in- terface - tras lockout supported - read data strobe supported (x8 only) - internal four bank operations with single pulsed ras description the v59c1512(404/804/164)q d is a four bank ddr dram organized as 4 banks x 32mbit x 4 (404), 4 banks x 16mbit x 8 (804), or 4 banks x 8mbit x 16 (164). the v59c1512(404/804/164)qd achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is designed to co mply with the following key ddr2 sdram features:(1) posted cas with additive la- tency, (2)write latency=read latency-1, (3)off-chip driv- er(ocd) impedance adjustment, (4) on die termination. all of the control, address, circuits are synchronized with the positive edge of an ex ternally supplied clock. i/o s are synchronized with a pair of bidirectional strobes (dqs, dqs ) in a source synchronous fashion. operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. a se- quential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. available speed grade: -5 (ddr2-400) @ cl 3-3-3 -37 (ddr2-533) @ cl 4-4-4 -3 (ddr2-667) @ cl 5-5-5 -25a (ddr2-800) @ cl 6-6-6 -25 (ddr2-800) @ cl 5-5-5 -19a(ddr2-1066)@cl 7-7-7 device usage chart operating temperature range package outline ck cycle time (ns) power temperature mark 60 ball fbga 84 ball fbga -5 -37 -3 -25a -25 -19a std. l 0c to 85c ? ?????? ? ? blank
2 v59c1512(404/804/164)qd rev. 1.3 may 2010 promos technologies v59c1512(404/804/164)qd pg 1 23 4 5 678910 11 12 13 14 15 161718 19 v 59 c 1 5 1280 4 q d j25 organization promos & refresh 64mx4, 8k : 25640 16mx16, 8k : 25616 32mx8, 8k : 25680 temperature 128mx4, 8k : 51240 32mx16, 8k : 51216 blank: 0 - 85 c 64mx8, 8k : 51280 i : -40 - 85 c type 256mx4, 8k : g0140 64mx16, 8k : g0116 h : -40 - 105 c 59 : ddr2 cmos 128mx8, 8k : g0180 e : -40 - 125 c speed 5 : 200mhz @cl3-3-3 voltage banks 37 : 266mhz @cl4-4-4 1 : 1.8 v 4 : 4 banks i/o 3 : 333mhz @cl5-5-5 8 : 8 banks q: sstl_18 rev code 25 : 400mhz @cl5-5-5 25a : 400mhz @cl6-6-6 19 : 533mhz @cl6-6-6 19a : 533mhz @cl7-7-7 special feature package l : low power grade rohs green package u : ultra low power grade description f j fbga p die-stacked fbga *rohs: restriction of hazardous substances *green: rohs-compliant and halogen-free 512mb addressing confi gura tion 128mb x 4 64mb x 8 32mb x1 6 #ofbank 444 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 ~a 13 a 0 ~a 13 a 0 ~a 12 column address a 0 ~a 9, a 11 a 0 ~a 9 a 0 ~a 9 ddr part number 3 promos technologies v59c1512(404/804/164)qd v59c1512(404/804/164)qd rev. 1.3 may 2010 x4 pack age pinout (top view) : 60ball fbga package notes: b1, b9, d1, d9 = nc for x4 organization. pins b3 has identical capacitance as pins b7. vddl and vssdl are power and ground for the dll. it is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. a b c d e f g h j k l vdd nc vss nc vssq dm vddq vddq vddq vssq vssq dqs dqs nc dq0 vddq dq2 vssq nc vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq dq1 dq3 nc vddl a1 a3 ba1 vref vss cke we ba0 123 789 vdd vss odt nc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 123456789 a b c d e f g h j k l ball locations (x4) : populated ball + : depopulated ball top view (see the balls through the package) 4 v59c1512(404/804/164)qd rev. 1.3 may 2010 promos technologies v59c1512(404/804/164)qd notes: 1. pins b3 and a2 have identical capacitance as pins b7 and a8. 2. for a read, when enabled, strobe pair rdqs & rdqs are identical in function and timing to strobe pair dqs &dqs and input masking function is disabled. 3. the function of dm or rdqs/rdqs are enabled by emrs command. 4. vddl and vssdl are power and ground for the dll. it is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. x8 package pinout (top view) : 60ball fbga package a b c d e f g h j k l vdd nu/ vss dq6 vssq vddq vddq vddq vssq vssq dqs dqs dq7 dq0 vddq dq2 vssq dq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq dq1 dq3 dq4 vddl a1 a3 ba1 vref vss cke we ba0 123 789 vdd vss dm/ rdqs rdqs nc odt + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ++ + + + 123456789 a b c d e f g h j k l + + ball locations (x8) : populated ball + : depopulated ball top view (see the balls through the package) 5 promos technologies v59c1512(404/804/164)qd v59c1512(404/804/164)qd rev. 1.3 may 2010 a b c d e f g h j k l vdd nc vss ldq6 vssq ldm vddq vddq vddq vssq vssq l dqs ldqs ldq7 ldq0 vddq ldq2 vssq ldq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 vdd a10 vss vddq vssq ldq1 ldq3 ldq4 vddl a1 a3 ba1 vref vss cke we ba0 123 789 vdd vss vdd nc vss udq6 vssq udm vddq vddq vssq udq1 udq3 udq4 vddq vddq vssq vssq u dqs udqs udq7 udq0 vddq udq2 vssq udq5 nc odt m n p r notes: vddl and vssdl are power and ground for the dll. lt is recommended that they are isolated on the device from vdd, vddq, vss, and vssq. x16 package pinou t (top view) : 84 ball fbga packa ge + + + + + + + + + + + 123456789 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r + + + + + + : populated ball + : depo pul ated ball top v i ew ball locations (x16) (see the balls through the package) 6 v59c1512(404/804/164)qd rev. 1.3 may 2010 promos technologies v59c1512(404/804/164)qd signal pin description pin type function ck ck input the system clock input. all inputs except dqs and dms are sampled on the rising edge of ck. cke input activates the ck signal when high and deactivates t he ck signal when low, thereby initiates either the power down mode, or the self refresh mode. cs input cs enables the command decoder when low and dis ables the command decoder when high. when the command decoder is disabled, new commands ar e ignored but previous operations continue. ras , cas we input when sampled at the positiv e rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a13 input during a bank activate command cycle, a0 -a13 defines the row address (ra0-ra13) when sampled at the rising clock edge for x4 and x8 and a0-a12 row address for x16 device. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends on the sdram organization: 128m x 4 ddr can = ca9, a11 64m x 8 ddr can = ca9 32m x 16 ddr can = ca9 in addition to the column address, a10(=ap) is us ed to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, aut oprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged simult aneously regardless of state of ba0 and ba1. ba0, ba1 input selects which bank is to be active. dqx ldqx,udqx input/ output data input/output pins operate in the same manner as on conventional drams. dq0-dq3 for x4 component, dq0-dq7 for x8 component and ldq0-ldq7 , udq0-udq7 for x16 component. dqs,(dqs ) ldqs,(ldqs ) udqs,(udqs ) rdqs,(rdqs ) input/ output data strobe, output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16 component, ldqs corresponds to the data on ldq0-ldq7; udqs coresponds to the data on udq0-udq7. for the x8, an rdqs option using dm pin can be enabled via the emrs(1) to simplify read timing. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complimentary signals dqs , ldqs , udqs , and rdqs to provide differ- ential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or dis- ables all complementary data strobe signals. in this data sheet, ?differential dqs signals? refers to any of the following with a10 = 0 of emrs(1) x4 dqs/dqs x8 dqs/dqs if emrs(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs if emrs(1)[a11] = 1 x16 ldqs/ldqs and udqs/udqs ?single-ended dqs signals? refers to any of the following with a10 = 1 of emrs(1) x4 dqs x8 dqs if emrs(1)[a11] = 0 x8 dqs, rdqs, if emrs(1)[a11] = 1 x16ldqs and udqs 7 promos technologies v59c1512(404/804/164)qd v59c1512(404/804/164)qd rev. 1.3 may 2010 dm, ldm,udm input in write mode, dm has a latency of zero and oper ates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high for x 16 ldm corresponds to data on ldq0-ldq7, udm corresponds to data on udq0-udq7. vdd,vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity. 1.8v +/- 0.1v vref input sstl reference voltage for inputs vddlq vssdl supply isolated power supply and gr ound for the dll to provide improved noise immunity. 1.8v +/- 0.1v odt input on die termination enable. it enables terminati on resistance internal to the dram. odt is applied to each dq, dqs, dqs and dm signals for x4 component and dq, dqs, dqs , rdqs, rdqs and dm for the x8 component. for x16 configurati on odt is applied to each dq, udqs/udqs , ldqs/ldqs , udm and ldm signal. odt will be ignor ed if emrs disable the function. rfu reserved for future use 8 v59c1512(404/804/164)qd rev. 1.3 may 2010 promos technologies v59c1512(404/804/164)qd self idle setting emrs bank precharging power writing act rda read srf ref ckel mrs ckeh ckeh ckel write automatic sequence command sequence rda wra read pr, pra pr refreshing refreshing down power down active with rda reading with wra active precharge reading writing pr(a) = precharge (all) mrs = (extended) mode register set srf = enter self refresh ref = refresh ckel = cke low, enter power down ckeh = cke high, exit power down, exit self refresh act = activate wr(a) = write (with autoprecharge) rd(a) = read (with autoprecharge) note: use caution with this diagram. it is indented to provide a floorplan of the possible state transitions simplified state diagram all banks precharged activating ckeh read write ckel mrs ckel sequence initialization ocd calibration ckel ckel ckel autoprecharge autoprecharge pr, pra pr, pra and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on-die termination, power down enty/exit - among other things - are not captured in full detail. 9 promos technologies v59c1512(404/804/164)qd v59c1512(404/804/164)qd rev. 1.3 may 2010 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the ba nk and row to be accessed (ba0, ba1 select the bank; a0-a13 select the row). the address bits registered c oincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device operation. power up and initialization ddr2 sdrams must be powered up and initialized in a pr edefined manner. operati onal procedures other than those specified may result in undefined operation. pow er-up and ini tialization seq uence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2*vddq and odt *1 at a low state (all other inputs may be undefined.) - vdd, vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95 v max, and - vref tracks vddq/2. or - apply vdd before or at the same time as vddl. - apply vddl before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. at least one of these two sets of conditions must be met. 2. start clock and maintain stable condition. 3. for the minimum of 200u s after stable power and clock(ck, ck ), then apply nop or deselect & take cke high. 4. wait minimum of 400ns then issue precharge all command. nop or desel ect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs(2) command, provide ?low? to ba0, ?high? to ba1.) 6. issue emrs(3) command. (to issue emrs(3) command, provide ?high? to ba0 and ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1 and a12.) 8. issue a mode register set command for ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0-1) 9. issue precharge all command. 10. issue 2 or more auto-refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll. 12. at least 200 clocks after step 8, execute ocd calibration ( off chip driver impedance adjustment ). if ocd calibration is not used, emrs ocd defaul t command (a9=a8= a7=1) followed by emrs ocd 10 v59c1512(404/804/164)qd rev. 1.3 may 2010 promos technologies v59c1512(404/804/164)qd calibration mode exit command (a9=a8=a7=0) mus t be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. *1) to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. programming the mode register for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time(twr) are user defined variables and must be programme d with a mode register set (mrs) command. addition- ally, dll disable function, driver impedance, additi ve cas latency, odt(on die termination), single-ended strobe, and ocd(off chip driver impedance adjustment) are also user defined variables and must be pro- grammed with an extended mode register set (emrs) command. contents of the mode register(mr) or extended mode registers(emr(#)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emr s variables, all variable s must be redefined when the mrs or emrs commands are issued. mrs, emrs and reset dll do not affect array contents, wh ich means reinitialization including those can be executed any time after power-up without affecting array contents. initialization sequence after power up /ck ck cke command pre all pre all emrs mrs ref ref mrs emrs emrs any cmd dll enable dll reset ocd default ocd cal. mode exit follow ocd flowchart 400ns trfc trfc trp trp tmrd tmrd tmrd toit min. 200 cycle nop odt tcl tch tis 11 promos technologies v59c1512(404/804/164)qd v59c1512(404/804/164)qd rev. 1.3 may 2010 ' ' 5 6 ' 5 $ 0 0 r g h 5 h j l v w h u 6 h w 0 5 6 7 k h p r g h u h j l v w h u v w r u h v w k h g d w d i r u f r q w u r o o l q j w k h y d u l r x v r s h u d w l q j p r g h v r i ' ' 5 6 ' 5 $ 0 , w f r q w u r o v & |